Senior ASIC Frontend Design Engineer Toàn thời gian

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Mô Tả Công Việc

Front End Engineers are mainly responsible for Front End tasks such as: RTL synthesis, STA, Power Analysis, Power Intent verification, Formal verification
Responsibilities include:
1. RTL/Netlist Audit
2. Power estimation and analysis
3. RTL synthesis
4. Formal verification
5. Timing signoff
6. RTL design and verification
7. Memory selection
8. Netlist handoff audit
9. Verify and develop timing constraints
Will work directly under a DM for a specific project.

Yêu Cầu Công Việc

Hands on experience with detailed exposure to an actual SoC design in
-STA
-Power Analysis
-Synthesis
-Formal verification

Use of Synopsys or Cadence EDA tools (Design Compiler, Prime Time, Tempus, Voltus)

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